This invention is in the field of integrated circuit manufacture. Embodiments of this invention are more specifically directed to the formation of capacitors in memory devices such as ferroelectric memories.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic devices and systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have been developed in recent years.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead-zirconium-titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits.
Non-volatile solid-state read/write random access memory (RAM) devices based on ferroelectric capacitors, such memory devices commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, have been implemented in many electronic systems, particularly portable electronic devices and systems. FRAMs are especially attractive in implantable medical devices, such as pacemakers and defibrillators. Various memory cell architectures including ferroelectric capacitors are known in the art, including the well-known 2T2C (two transistor, two capacitor) cells, among others. Ferroelectric capacitors are also implemented in some integrated circuits as programmable analog capacitors.
FIG. 1a illustrates the construction of an example of a portion of an integrated circuit including a portion of a ferroelectric random access memory (FRAM). In this example, ferroelectric capacitor 15 and metal-oxide-semiconductor (MOS) transistor 17 are disposed at or near a semiconducting surface of a semiconductor substrate, although capacitor 15 and transistor 17 may instead be formed at the surface of a semiconductor layer that overlies an insulator layer, such as according to a silicon-on-insulator (SOI) technology as known in the art. In the example of FIG. 1a, isolation dielectric structures 11, gate electrode 16, and n-type source/drain regions 14 are disposed at or near the surface of substrate 10, in the conventional manner for MOS integrated circuits. N-channel MOS transistor 17 in the example of FIG. 1a includes n-type source/drain regions 14 at the surface of p-type substrate 10 (or of a p-type “well” formed into substrate 10, as the case may be), with gate electrode 16 overlying a channel region between source/drain regions 14, and separated from the channel region by a gate dielectric, as conventional. Interlevel dielectric 12 is disposed over transistor 17, with conductive plug 13 disposed in a contact opening through interlevel dielectric 12 to provide a conductive connection between one of source/drain regions 14 of transistor 17 and lower plate 20a of ferroelectric capacitor 15.
In the example of FIG. 1a, ferroelectric capacitor 15 is formed of a ferroelectric “sandwich” stack of conductive plates 20a, 20b, between which ferroelectric material 22 is disposed. Lower plate 20a is formed at a location overlying conductive plug 13, as shown in FIG. 1a, so as to be in electrical contact with the underlying source/drain region 14 by way of conductive plug 13. Lower conductive plate 20a and upper plate 20b are formed from one or more layers of conductive metals, metal oxides, and the like. A typical construction of lower conductive plate 20a is a stack of a diffusion barrier layer in contact with conductive plug 13 and a layer of a noble metal (e.g., Ru, Pt, Ir, Rh, Pt, Pd, Au) or metal oxide (e.g., RuOx, IrOx, PdOx, SrRuO3) overlying the barrier layer and in contact with the ferroelectric material 22. Conductive plates 20a, 20b are typically formed of the same conductive material or materials as one another, for purposes of symmetry, simplicity of the manufacturing flow, and improved ferroelectric polarization performance.
As mentioned above, ferroelectric material 22 in this conventional transistor 15 is typically lead-zirconium-titanate (PZT) or strontium-bismuth-tantalate (SBT), deposited by way of metalorganic chemical vapor deposition. Ferroelectric material 22 in capacitor 15 is desirably as thin as practicable, for purposes of electrical performance (e.g., polarization), and for consistency with the deep sub-micron features used to realize modern integrated circuits.
By way of background, conventional manufacturing process flows for the fabrication of CMOS integrated circuits include a thermal treatment process, following the formation of transistors 17, that has the effect of stabilizing the electrical characteristics of transistors 17. This thermal treatment (also commonly referred to as an “anneal” or “sinter”) is typically performed by heating the wafer to an elevated temperature in a hydrogen-bearing atmosphere for a selected duration of time. An example of such a thermal treatment is the heating of the wafer to about 435° C. for about ten minutes in a flow of “forming gas” (i.e., a mixture of hydrogen and nitrogen), followed by twenty minutes at about 435° C. in a flow of pure hydrogen. For CMOS integrated circuits, this thermal treatment has been observed to substantially reduce the variation in transistor electrical characteristics (e.g., threshold voltage) from die-to-die on the same wafer, and from wafer-to-wafer within a manufacturing lot. In conventional CMOS manufacturing flows, this thermal treatment is typically performed at a later stage in the process, for example after formation of metal conductors and prior to the deposition of a protective overcoat layer. It is believed that this thermal treatment causes hydrogen ions to passivate charge trapping sites in the gate regions of the MOS transistors, which reduces transistor threshold voltage variation caused by intra-wafer and inter-wafer defect density variations.
However, it has been observed that this thermal treatment in a hydrogen-bearing atmosphere degrades the polarization characteristics of ferroelectric material 22, particularly for the case of PZT. This deleterious effect necessitates omitting the hydrogen anneal thermal treatment from the conventional process flow in the manufacture of CMOS integrated circuits containing ferroelectric capacitors, such as FRAM integrated circuits. The resulting variation in transistor electrical characteristics among a population of these devices as manufactured may require some yield loss to be tolerated, or may necessitate relaxation of design specifications (circuit performance, device sizes, etc.) from what may otherwise be attainable for the technology node.
One conventional approach toward addressing this threshold voltage variation is the use of a targeted threshold adjust ion implantation to shift the threshold voltage distribution so as to better tolerate the variation if the thermal treatment is not performed. However, as known in the art, this technique is not available for integrated circuits that include MOS transistors of the “drain-extended” type (i.e., “DEMOS” transistors), as are common in modern integrated circuits intended for high voltage applications.
FIG. 1b illustrates, in cross-section, an example of an integrated circuit including such a DEMOS transistor 17′. DEMOS transistor 17′ is constructed similarly to transistor 17 of FIG. 1a, but in this example is not connected directly to an instance of ferroelectric capacitor 15, as is typical for integrated circuits including both DEMOS transistors and embedded FRAM arrays (the FRAM cells typically do not involve the high voltages for which DEMOS transistors are needed, especially considering the additional chip area required for the DEMOS transistors). In this instance of n-channel DEMOS transistor 17′, source/drain regions 14, 14′ are heavily-doped n-type, as in transistor 17 of FIG. 1a. However, drain region 14′ is not disposed adjacent to the channel region of transistor 17′. Rather, n-type drain drift region 19 is disposed at the surface of substrate 10, between the more heavily doped n-type drain region 14 and the channel region underlying gate electrode 16. N-type drain drift region 19 is lightly-doped relative to the heavily-doped n+ drain regions 14, 14′, as known in the art. The presence of drain drift region 19 reduces the vulnerability of transistor 17′ to hot carrier degradation, particularly in high voltage applications. As such, DEMOS transistors are attractive in higher-voltage applications, considering that modern sub-micron non-DEMOS transistors are restricted to relatively low voltages (e.g., on the order of one volt).
However, conventional manufacturing methods do not provide independent control of the threshold voltage of DEMOS transistors. As such, the targeted threshold adjust implant cannot address threshold voltage variation among DEMOS transistors if the use of a hydrogen anneal to reduce the variance in transistor characteristics is precluded by the ferroelectric devices, as discussed above. Accordingly, integrated circuits having both DEMOS transistors and ferroelectric capacitors must be designed with sufficient design margin so as to tolerate a relatively wide variation in transistor characteristics. This re-specification of the design necessarily results in less-than-optimal circuit performance or larger chip area requirements.